LSI Functional Verification Service
The keys to functional verification are “verification strategy” and “highly complete verification item extraction.” Our functional verification services emphasize highly complete verification item extraction while also generating test benches and functional scenarios, random verification, and even functional coverage to meet customer demands by providing these services from a wide variety of angles. By implementing functional verification on the RTL and C models designed by customers from a third-party perspective, we improve quality of customers’ circuits.
Verification Item Extraction Services
In our verification item extraction services, we propose the optimal verification strategy for our customers while also providing verification item extraction services using the methodology in the IP Functional Verification Guide developed by STARC (Semiconductor Technology Academic Research Center). We use our customer’s functional specification as the interface.
Random Verification Services
We perform random verification and coverage-driven verification that make full use of cutting-edge verification methodologies. Our verification methodologies apply to OVM, VMM, and UVM. We implement random verification in an optimal verification environment to our customers’ design environment and design tools.
System Verification Services
While verifying the operation of the SoC systems designed by our customers with use case, we carry out functional verification of these systems.
By collecting necessary information, such as the number of transactions and the latency with the functional monitor, we understand the bottlenecks, such as the memory transfer concentration on ahead, then feed it back to the demand specifications and functional specifications.
We optimize the operations as our customers’ own systems.
In recent years there has been remarkable progress on FPGA, and with the large scale number of gates on mass-produced types. The lengthening of evaluation and verification times to activate the normal operation of FPGA is seen as problematic and has become a serious obstacle for time to market in product development.
In our FPGA design quality improvement services, we consider a variety of aspects of FPGA development, including automatic RTL generation from specifications, verification item extraction and simulation, performance assessment, CDC verification of asynchronous circuits, and streamlining debug of firmware using verification platforms.
Automatic RTL Generation From Specifications
By inputting specifications in our specific format, top-connected RTL and register are automatically generated. We support both short TAT (Turn Around Time) and quality in FPGA design.
*We plan to release assertion and generation of the various UCF files for FPGA development tools in the near future.
FPGA Verification Services
We improve the FPGA design quality with SoC verification methodology in the FPGA design. Also, by using generated test benches, we can evaluate performance and make early determination of specifications.
Asynchronous Circuit (CDC) Verification Services
There are a variety of problems that can occur with asynchronous circuits, such as metastabe, reconvergence problems, data loss problems, and etc. When these problems occur, the causes are difficult to be analyzed due to irregularity and irreproducibility of these problems. As a result, they can have a significant impact on development schedules.
Because we perform formal verification, we can solve asynchronous circuit problems without simulation.
For customers who cannot purchase expensive formal verification tools, we perform asynchronous circuit (CDC) verification to verify the locations that violate synchronization rules, making it possible to resolve problems at the design stage.
Firmware Verification Platform Construction Services
We can accelerate firmware development by using a firmware verification platform to perform co-verification of hardware and software.
We prepare a simulation environment to verify firmware with real equipment response, so the board evaluation time can be dramatically shortened. We support both SystemC and SystemVerilog.